I can find all kinds of information on calling a script from a makefile but not the other way around.I'm writing a VERY basic shell script, and I need to call a makefile located in a directory lower than the shell script but can't seem to figure it out../dir/make and ./dir/makefile don't work.
I'm aware that one can export make variables to other makefiles; however, how does one export them to the environment of $(shell)? Take the example below:
Code: export TEST VARIABLE=$(shell echo $$TEST) .PHONY: all all: #$(VARIABLE)
In this example, I might call make TEST=test. The goal is for $TEST to be available to the environment of the shell escape. This is because I need its value in a script which is called. For example:
Code: VARIABLE=$(shell i-need-TEST.sh)My current solution is the following:VARIABLE=$(shell export TEST="$(TEST)"; i-need-TEST.sh) but this only works if I know all if the variables needed at that point (as opposed to being able to export variables in included makefiles.) Is there an easy solution?
I've got a CGI that I'm trying to debug. Apache gives me an ambiguous 500 error; it would be nice to see the raw output via the shell. I've got the POST request w/headers as follows. What's the best way to troubleshoot this?
POST /cgi/packBoxes.cgi HTTP/1.1 Host: 70.87.60.214 User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.0.10) Gecko/2009042316 Firefox/3.0.10 (.NET CLR 3.5.30729) Accept: text/html,application/xhtml+xml,application/xml;q=0.9,*/*;q=0.8
i used ldap for authentication.now i have a perl script that users use it for login(contact.pl),then this script calls a shell script(ip.sh) for create iptables chain.
when i call that into contact.pl ,it just prints: usr/sbin/iptables but ip chains didn't change.what is problem? whenever run ip.sh in bash it works correctly
I am trying a scenario for calling a shell script when ever a trigger is called. Can some one guide me how to achieve this scenario. Also it should passes the value from the table to the shell script. Can some one explain me along with the example.
I have a QNX machine with a slinger webserver running on it. With a cgi script i'm trying to do the QNX cksum call and compare it's output value with a fixed output. When i execute the script at the command line it works perfect, but when execute this script by by the webserver in my browser it doesn't work. Here's my code:
I have a script that I would like to run when my laptops connects to a new network (e.g. changes to another SSID). I've done some searching on the net but could not find any suitable solution (but I bet there is).
I just downloaded slackware 13.1(x86) and i'm trying to compile ndiswrapper-1.56 using the slackbuild from slackbuils.org and i'm getting this error:
Code:
Makefile:535: /usr/src/linux-2.6.33.4/arch/i486/Makefile: No such file or directory make[2]: *** No rule to make target `/usr/src/linux-2.6.33.4/arch/i486/Makefile'. Stop. make[1]: *** [modules] Error 2 make: *** [all] Error 2
I want to gave much details as possible. working directory (~/a1/shell) in the shell directory i have Makefile. also in the shell directory i have subdirectory's (obj, src, include)
My current Makefile
Quote:
#What needs to be built to make all files and dependencies
clean:
# End of Makefile
I wanted it so: all .o files are created in the obj subdirectory, and my application, sshell, is created in the shell directory.
I am getting this error when i run the make run: No rule to make target 'shell.h', needed by 'shutil.o'. stop
In practice I have a script that call a java program that call a linux system command. The script if I run it, from a shell functions well,so it is not a java problem. The problem come out when i put this script in a crontab schedulation. The result in this case is that java do not execute the system command. I think it depends on crontab
Is it possible to debug a makefile? In a bash script I can use "set -x" so that all variables are shown with their values. I am looking for such feature in makefile to see the variables and their values.
in directory a_dir, have a file named a_file.i can type "source a_file" under directory a_dir and execute successfully.but if i write the command to a Makefile under directory b_dir, the "source" function can't be executed well. it will generate some error message like this:
./a_file: line 1: setenv: command not found ./a_file: line 2: setenv: command not found ./a_file: line 3: setenv: command not found ./a_file: line 5: setenv: command not found
I want to write simple non recursive makefile, but I am not getting syntax of it. Please give me example with simple description. I had read docs, html's but I am not getting how that works please give simple example. consider I have following directory structure.
I need to write an else-if condition in a makefile, and though the format is posted on several websites, nothing seem to be working, andI get an error everytime. Could anybody please write a small example with an else-if conditional in a maekefile?
I've been trying to figure out how to use make and makefile to compile and link some .cpp/.h. All i seem to find on google says to read the README for the software. But this is my own created c++ project. Im just looking for a simple makefile for my own .cpp/.h files( about 20 total).
I have tried using 2 different makefile "examples" as a template, but neither worked. I am getting error saying "file1.cpp: no newline character at end of file". or something to that degree.
Does anyone know if it is possible to make rules in a Makefile that would work like this:
> make debug module or > make module debug
where module can be any module that has a specific rule in the Makefile.
The thing I have is a Makefile with different rules that I compile like this:
> make module
What I would like is to add an option so I can compile whichever module with debug-information just by adding a debug to the make command. The debug-information I know how to do, the problem is how to make the Makefile work...
I would like to set run time library path in my makefile, so that my exe should search run time libraries in that path when executed. How to set this in makefile?
I want to install pgplot on ubuntu 9.10 but I have some errors after editing makefile in line 880
replaced "pndriv.o : ./png.h ./pngconf.h ./zlib.h ./zconf.h" by "pndriv.o : /usr/local/include/png.h /usr/local/include/pngconf.h /usr/local/include/zlib.h /usr/local/include/zconf.h" and running code "make" I get this error : No rule to make target `/usr/local/include/png.h', needed by `pndriv.o'. Stop. also I tried to uncomment this line got another error : make: *** [pndriv.o] Error 1 and also replace "pndriv.o : ./png.h ./pngconf.h ./zlib.h ./zconf.h" by "pndrive.o : " what should I do ?
I am new to creating make files. I have been able to create simple makefiles for those applications which do not involve database but am unable to create for the ones that do involve database.
That's how my make file looks
Code:
clean:
tar:
There is no error in the code because when I compile the code through the following command, it gives me no error
Code:
The error msg is:
Code:
Where am I going wrong? Am I not providing the correct mysql path?
I am new to Linux and I am trying to install a C program from source using Makefile. So I 've created a "hello world" program and then a Makefile to install it. Then I logged in as root and used make install
The following error occurs: make: execvp: /usr/bin: Permission denied make: *** [install] Error 127
Here is the Makefile: CC=gcc CFLAGS=-c -Wall PROGS = hello INSTDIR = $(prefix)/usr/bin/ INSTMODE = 0755 INSTOWNER = root INSTGROUP = root
all: $(PROGS) $(PROGS): main.o $(CC) main.o main.o: main.c $(CC) $(CFLAGS) main.c install:$(PROGS) $(INSTALL) $(INSTDIR) $(INSTALL) $(INSTMODE) $(INSTOWNER) -o $(INSTGROUP) $(PROGS) $(INSTDIR) clean: rm -rf $(PROGS) *o $(PROGS) So, where are the errors
As part of an assignment, our class was given a small set of c++ classes which are compiled using a makefile. As part of the assignment, I have created a namespace and saved in it a .cpp file. The functions, constants and typedefs from the namespace are now used in one of the original files, and so I added an <#include MyFile.cpp> to the file I modified, in addition to a using MyNamespace;
When I try to use the original makefile, the compiler gives a lot of errors about multiple definitions of every function in the namespace. What do I need to do to resolve this? Do I need to change the makefile or one of the files themselves? I am new to Linux programming and makesfiles.
MACHINE: HP Proliant DL260G5OS: SLES 11 SP1kernel: Linux xserver 2.6.32.12-0.7-default #1 SMP 2010-05-20 11:14:20 +0200 x86_64 x86_64 x86_64 GNU/LinuxIt is used as remote xserver in a LAN.I have configured /usr/lib/restricted/bin/.rbashrc with some environment variables but when the users logon in the system finally is executed $HOME/.bashrc and some environment vars are overwritten.
I have ~200 c files in my makefile[$(SRCS)], and it compiles all of the files using a single gcc command. So each time I make a change in one c file, it ends up re-compiling all the files, then linking to make the binary. How can I break out the compilation into individual gcc commands for each c file, so that make checks the timestamp and accordingly compiles only the modified files.