but I want to run the applications in another pc, so I have used the option --prefix=/some/directory/ when executing ./configure, so I could just copy this folder to the other pc. However, my programs now need to have libraries and shared files in the same location that I used with --prefix, instead of /lib, /usr, etc.
I just downloaded slackware 13.1(x86) and i'm trying to compile ndiswrapper-1.56 using the slackbuild from slackbuils.org and i'm getting this error:
Makefile:535: /usr/src/linux-184.108.40.206/arch/i486/Makefile: No such file or directory make: *** No rule to make target `/usr/src/linux-220.127.116.11/arch/i486/Makefile'. Stop. make: *** [modules] Error 2 make: *** [all] Error 2
I am a beginner in Linux. Never did any kernel programming in Linux/Windows before. I am now on a project and I am supposed to understand a Linux Device Driver Code. It contains 6 .c files and 1 Makefile.
The make file goes as this:
I have a.c b.c c.c d.c d.c e.c f.c in the director along with the Makefile mentioned.
When I put a "test" target in my Makefile containing Code: @echo "CXX= $(CXX)" it tells me "CXX= g++". But I have nothing in the Makefile assigning any value to CXX, and as far as I can tell I have no CXX environment variable (no "CXX" appears when I run the shell command "env", and "echo $CXX" returns a blank line. So where's the g++ value coming from. Is this just built into Gnu Make, or is there a configuration file for make somewhere?
I am trying to run a script to setup environment variables and then run other commands in a make file. But the source or the dot operator (shell is bash) does not seem to take any effect as the subsequent command didn't pick the environment up. Do I have to put every lines of the environment setup in the first script into the makefile instead?
I am trying to use a software package written in ANSI C. It has a makefile which has to be executed first.
As soon as I execute it I get messages like: line i: command not found.
Commands for which I am getting errors :
CC = /usr/bin/gcc GCCFLAGS = -c -Wall ROOTDIR = .
My gcc compiler is located in the above directory only. In ROOTDIR also I tried giving the path in which all the required files & folders are present but still I get the command not found error in all the lines.
It builds fine when I build from the command line ( make -f sample.mk).
However, it does not build when building from eclipse (which essentially calling the same makefile). The make output shows exactly the same as what I got from the command line build, except the last line showing
I'd like to write a Makefile for my CUDA/C++ code but I didn't know how things work with CUDA, I mean there is a nvcc compiler but I don't know what I've got to do with this. Do I have to firstly run nvcc and then g++ or only nvcc to compile my CUDA/C++ code ? I found nothing on the web explaining such basic things .
So I have been trying for 8 hours to try to get the index of an element from a list in a Makefile. The problem is that after I get the index using all the methods I have tried, the index cant be used in the "word" function:
for instance: $(OUTPUT2) : INDEX = $(shell echo $(OUTPUT2) | sed -r -e "s/[ ]+/ /g" | grep -n $@ | sed 's/^([0-9]*):.*/1/')
will create a variable INDEX defined specifically for each member of OUTPUT2, so that each output knows its index. Unfortunately, when I pass this $(INDEX) into word, it doesn't work:
$(OUTPUT2) : $(word $(INDEX), $(INPUT1)) $(word $(INDEX), $(INPUT2)) echo $(INAME) $(TMPBASE) $@ and I get the error: Makefile:16: *** non-numeric first argument to `word' function: 'num'. Stop.
I feel like if I could just convert a string to a Makefile acceptable number this would just work....
im trying to write a makefile which contains :two cpp files and two header files. now i've put cppfiles in a folder called source whose path is: /root/workspace/source and header files in a folder called header whose path is:
my makefile is in the path:/root/workspace/makedemo my makefile was like this:
HEADERS = $(shell /root/workspace/makedemo/header ls *.h) SOURCES = $(shell /root/workspace/source ls *.cpp) COMPILERFLAGS = -W -Wall DEBUGFLAGS = -g
im sure that i've given the correct path but it is showing errors like this:
[root@localhost makedemo]# make /bin/sh: /root/workspace/source: is a directory /bin/sh: /root/workspace/source: is a directory g++ -W -Wall -I. -o output g++: no input files make: *** [output] Error 1
I'm trying to make recursive makefile work but it's giving me two problems. I have a top folder with the main Makefile and one Makefile for each sub folder 'one' and 'two'. Makefile in subfolder 'one' and 'two' are identical. The top Makefile (still a bit messy) looking like this:
Code: # Directories CC = gcc CFLAGS = -Wall -Wextra TARGET_DIR = bin MAIN_FILE = one.c
I am dealing with one FORTRAN 90 code, have made small changes.
milenko@milenkons:~/mt4$ make mt4 make: 'mt4' is up to date. milenko@milenkons:~/mt4$ ifort -c MT2DDIB1.FOR milenko@milenkons:~/mt4$ make mt4 make: 'mt4' is up to date. milenko@milenkons:~/mt4$ make mt4 make: 'mt4' is up to date. milenko@milenkons:~/mt4$ make mt4 make: 'mt4' is up to date.
I go for make command but it does not see that the source code has been modified.Than I do compilation from command line,try make again but no use. F95=ifort FFLAFGS= -O1
I'm aware that one can export make variables to other makefiles; however, how does one export them to the environment of $(shell)? Take the example below:
Code: export TEST VARIABLE=$(shell echo $$TEST) .PHONY: all all: #$(VARIABLE)
In this example, I might call make TEST=test. The goal is for $TEST to be available to the environment of the shell escape. This is because I need its value in a script which is called. For example:
Code: VARIABLE=$(shell i-need-TEST.sh)My current solution is the following:VARIABLE=$(shell export TEST="$(TEST)"; i-need-TEST.sh) but this only works if I know all if the variables needed at that point (as opposed to being able to export variables in included makefiles.) Is there an easy solution?
I am new to the whole concept of makefiles, and I'm trying to compile and build my program using a makefile template I have found. My project consists of three directories: "source", where my .cpp files are (source1.cpp, source2.cpp, source3.cpp), "include", where my .h files are (header1.h, header2.h, header3.h), and "obj", where the object files are to be stored (obj1.o, obj2.o, obj3.o). In the project root directory is my makefile, which is as follows:
Code: EXEC = myexe CC = g++ IDIR = include SDIR = source ODIR = obj
I'm having problems with compiling recursive Makefiles in my directory structure: My folder layout is: top/|- one/|- one.c (With main function)|- zero.c|- two/|- two.cin my top folder the make file looks like:
Code: MAKE_DIRECTORIES = one two .PHONY: all all: $(MAKE_DIRECTORIES)
.PHONY: $(MAKE_DIRECTORIES) $(MAKE_DIRECTORIES): @echo $@ $(MAKE) --directory=$@ in my one and two folder I have the following Makefile:
Code: .PHONE: all all: @echo $@ $(CC) $(CFLAGS) *.c But when I compile it from top folder: make
I get following output: Code: one two Which states that directory statement by echo in main Makefile is ok but the files are not compiled in one and two.
I'd like to create a target named "debug" or something similar which will use some special optimization flags useful when debugging (for example -ggdb). At the moment my makefile is neat (which I like) and looks like