Hardware :: Using Triple-channel Memory Architecture?

I am wondering just how the triple channel memory architecture, like found in various socket 1366 CPUs, including i7, works. For maximum speed in close locality accesses, in theory it would need to interleave at the memory access width (64 bit?).But interleaving at a multiple of 3 is what looks odd. A multiple of 2 or 4 would be trivial, by just using the lowest 1 or 2 bits (of the access word address), to select with part of the interleave stride. But a multiple of 3 would mean doing an arithmetic division by 3 and using the modulus, for each memory cycle. Can it really do that, that fast?

Or is something else going on where it approaches having a perfect interleave, but not quite, in order to keep the operation speed at maximum (e.g. some simpler kind of arithmetic that can keep up with a slightly slower memory speed that results from a less than perfect interleave)?

Also, I was reading somewhere where someone suggested that if you put 2 DIMMs in one channel, and 1 DIMM each in the other two channels (where all DIMMS are the same size), it will operate in triple channel mode for 3/4 of the memory address space, and in single channel mode for the remaining 1/4 of memory. Is it designed to do that? Is there an advantage doing that instead of putting 2 DIMMs in the 1st channel and 2 DIMMs in the 2nd channel, and leaving the 3rd channel empty (e.g. getting only double-channel speed, but doing so for all of memory)?

IWSTM that if I'm running multiple threads or hyperthreads, these may be accessing memory at sufficiently widely arranged locations (depending on virtual memory page placement) that even if there is no interleave at all, there can be some improvement.